DYNANIC to demonstrate programmable 400G Ultra Ethernet RDMA at AI Infra Summit 2026

25 Aug 2026

DYNANIC to demonstrate programmable 400G Ultra Ethernet RDMA at AI Infra Summit 2026

Stand: Start Up Zone

Tomáš Fiala, Online Marketing Specialist, DYNANIC, fiala@dyna-nic.com

San Jose, United States – 25th August, 2026 – DYNANIC, a provider of high-performance FPGA-based networking solutions, announced that it will demonstrate one of the first publicly disclosed FPGA-based implementations of Ultra Ethernet RDMA operating at 400 Gbps at the AI Infra Summit 2026, taking place September 15 to 17 at the Santa Clara Convention Center in Santa Clara, California.

The demonstration shows how DYNANIC’s RDMA module, running on the Silicom ThunderFjord FPGA card built around the Altera® Agilex® 7 SoC FPGA M-Series, delivers standards-based Ultra Ethernet communication at up to 400 Gbps per card in each direction. As the first Ultra Ethernet-capable silicon products begin to reach the market, DYNANIC provides an FPGA-based alternative whose data path remains reprogrammable after deployment. This allows operators to evaluate Ultra Ethernet today and adapt the implementation as the specification and workload requirements evolve.

Ultra Ethernet RDMA at 400G

DYNANIC’s RDMA module places acceleration directly into the data path at 100G, 400G, and beyond, with full Ultra Ethernet support exposed through the standard libfabric API.

The module enables organizations to:

● Run standards-based Ultra Ethernet RDMA communication at up to multiple 400 Gbps per card in each direction

● Reduce idle time during synchronization and shorten training and inference runs

● Integrate through the standard libfabric API, without FPGA development on the customer side

● Adopt future Ultra Ethernet revisions as firmware updates on hardware already installed

In large training and inference clusters, raw bandwidth is only part of the problem. Collective operations force compute nodes to wait for one another, and every stall in the fabric during synchronization becomes idle at compute time. When the interconnect cannot sustain lossless, low-latency operation under real job traffic, cluster utilization falls and job completion time grows regardless of how much compute is installed.

RoCEv2 has enabled broad adoption of RDMA over Ethernet, but standard RoCEv2 was not designed for the synchronized, burst-heavy traffic patterns of today’s largest AI clusters. At scale, it often requires carefully engineered lossless fabrics and Priority Flow Control, which can introduce head-of-line blocking and spread congestion across the network.

Ultra Ethernet modernizes RDMA with mechanisms including multipath packet spraying, flexible packet ordering, selective retransmission, and more scalable congestion control. It is designed to operate efficiently over both lossless and best-effort Ethernet networks, making the transport more resilient to the traffic patterns generated by distributed AI workloads as outlined in the technical paper Ultra Ethernet’s Design Principles and Architectural Innovations.

Ultra Ethernet defines how that communication should behave. DYNANIC implements the specification inside an FPGA-based, multi-purpose packet processing pipeline, which means the data path remains programmable after deployment. Operators adopting Ultra Ethernet on fixed-function silicon depend on the next hardware generation for every specification revision. With DYNANIC, the same card follows the standard as it evolves.

The module targets AI training and inference clusters, high-performance computing environments, and research computing centers where the fabric determines how efficiently the installed compute is used.

Key technical highlights

● Throughput: Up to 2x 400 Gbps per card in each direction over PCIe 5.0 x16.

● Data rate: 10 million IOPS at 4 kB payloads, 20 million IOPS at 2 kB payloads.

● Latency: Signaling in the nanosecond range, data transfer in the microsecond range.

● Compatibility: Full Ultra Ethernet support exposed through the standard libfabric API.

● Lifespan: Updates to future Ultra Ethernet versions are delivered as FPGA firmware, without replacing hardware.

Relevance to AI and HPC infrastructure

As AI clusters scale toward terabit-scale interconnects, operators require a fabric that delivers not only bandwidth, but also predictable, lossless behavior under the synchronization traffic that collective operations generate. Utilization and job completion time are decided in the network as much as in the compute.

DYNANIC’s FPGA-based approach combines line-rate packet processing with a programmable data path, allowing infrastructure to follow standards as they are ratified rather than waiting for the next silicon generation. Because the platform is exposed through standard interfaces and runs across multiple FPGA families and card vendors, operators gain hardware-level performance without committing their cluster to a single vendor roadmap and without building FPGA expertise in-house.

DYNANIC is currently testing the module with selected early customers to validate integration, interoperability, and performance under representative AI and HPC workloads.

Live demonstration at AI Infra Summit 2026

DYNANIC will demonstrate the solution live at Start UpZone 1011. A two-port FPGA card simulates two nodes, with one port transmitting and the other receiving, while live statistics show the ongoing Ultra Ethernet communication. The planned interactive demonstration will present real-time Ultra Ethernet communication statistics. Subject to final development, visitors will also be able to adjust selected parameters, such as payload size, and observe their effect on performance.

AI Infra Summit brings together the full stack of AI infrastructure (compute, interconnect, data center, and storage), placing the interconnect discussion in front of the engineers and infrastructure leaders who own cluster utilization targets.

Executive quotes

"Ultra Ethernet is still evolving, which makes a programmable implementation especially valuable. By placing the transport in an FPGA-based packet-processing pipeline, we can refine its behavior, support future revisions through firmware, and expose the solution through the standard libfabric interface without requiring customers to redesign their applications or develop FPGA expertise. AI infrastructure should not be locked to yesterday’s hardware roadmap. We enable operators to adopt Ultra Ethernet now and keep adapting it after deployment."

said Lukáš Kekely, Chief Technology Officer, DYNANIC.

“By bringing together Altera’s Agilex™FPGA, Silicom’s ThunderFjord platform, and DYNANIC’s packet-processing pipeline, we see a powerful example of how FPGA acceleration can reshape networking. This is precisely the kind of breakthrough the market is hungry for: solutions that unlock scalability and efficiency to keep pace with the exponential growth of AI networking,”

said Mark Moran, Director of Adoption and Acceleration Group at Altera.

“Ultra Ethernet is moving quickly from specification to deployment, and customers need complete solutions, not more components to integrate. By combining Silicom’s hardware platform with DYNANIC’s packet processing pipeline, we’re giving customers a practical path to bring Ultra Ethernet connectivity to market faster.”

said Henrik Lilja, VP Strategic Technologies, Silicom

About DYNANIC

DYNANIC is a company founded by researchers and engineers with more than two decades of experience in FPGA-based network acceleration. The company develops high-performance and highly adaptable networking solutions that help infrastructure scale, evolve, and maintain predictable performance using a unique 400G approach.

DYNANIC simplifies FPGA adoption through ready-to-integrate software interfaces and programmable packet-processing technology, enabling customers to deploy hardware-accelerated networking without the complexity traditionally associated with FPGA development.

For more information, visit dyna-nic.com/our-story.

About Silicom

Silicom Ltd. is an industry-leading provider of high-performance networking and data infrastructure solutions. Designed to optimize performance and efficiency in Cloud, Data Center and Edge environments, Silicom’s solutions increase throughput and minimize latency, serving as the infrastructure backbone for today’s most critical technologies. Their innovations empower high demand workloads across Artificial Intelligence (AI) inference, SD-WAN, SASE, cyber security, fabric switching, NFV, and more.

Their comprehensive portfolio, including high-speed server adapters, advanced hardware offloading and acceleration engines, AI NICs, FPGA-based smart cards, Post Quantum Cryptography (PQC) hardware accelerators, white label switches and Edge CPEs, is used by Tier-1 customers throughout the world, including cloud players, service providers and OEMs, to enable their networks to scale efficiently. With engineering excellence, a strong financial position and a legacy of over 400 active Design Wins, Silicom serves as the "go-to" connectivity and performance partner for technology leaders around the globe, and drives the next generation of infrastructure. For more information, please visit: www.silicom.co.il

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