HyperAccel Advances Energy- and Cost-Efficient AI Inference with LPU Architecture

Designed specifically for LLM inference workloads, HyperAccel’s LPU takes a different approach to AI acceleration by optimizing memory access and data movement rather than relying solely on higher compute performance or high-bandwidth memory.

Its flagship Bertha accelerator uses 192GB of LPDDR5X memory, 546 GB/s of aggregate memory bandwidth, and a proprietary Streamlined Memory Access architecture designed to achieve approximately 90% effective memory-bandwidth utilization during inference. Bertha operates at a 250W TDP and is designed for deployment in standard data center server environments through a PCIe Gen5 interface.

By optimizing how data moves between memory and compute, the architecture is designed to improve token-generation efficiency while reducing power consumption and total infrastructure cost for LLM inference.

HyperAccel is also developing its LPU technology for edge and on-device AI, extending its inference-focused architecture beyond data center environments.

At AI Infra Summit 2026, visitors can meet the HyperAccel team and learn more about its LPU architecture, Bertha accelerator, and approach to building more efficient AI inference infrastructure.