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17 Sep 2026
SignatureIP Unveils IP Library for Chiplet-based AI, HPC and Data Center Systems at AI Infra Summit 2026
SANTA CLARA, Calif. - September 17, 2026 - SignatureIP today announced the general availability of a comprehensive library of Interconnect, Interface and System-on-Chip (SoC) Subsystem IP purpose-built for chiplet-based systems targeting artificial intelligence, high-performance computing (HPC) and data center applications. The announcement was made at AI Infra Summit 2026, held September 15–17 at the Santa Clara Convention Center.
As AI and HPC workloads push single-die silicon past its practical limits, chip architects are turning to chiplet-based, disaggregated designs to scale compute, memory and I/O subsystems independently. SignatureIP's portfolio offers system architects a single IP foundation to design coherent, low-latency, high-throughput chiplet systems – from architecture through tape-out. As a part of this program, SignatureIP works with its ecosystem partners to provide a complete solution to mutual customers.
“AI accelerators and chips put a renewed focus on efficient, high-performance interface IP and, by extension, require the highest-performance, hardware-assisted verification and validation tools like Siemens’ Veloce CS suite of emulation and prototyping technology,” said Jean-Marie Brunet, senior vice president and general manager, Hardware Assisted Verification, Siemens Digital Industries Software. “It is therefore exciting to see IP providers like SignatureIP take full advantage of the unique capabilities of Siemens’ Veloce CS Emulation and prototyping solutions to validate and gain certification for their PCIe, CXL and Ethernet IP. It highlights the convergence of essential technologies for next-generation AI hardware.”
Interconnect: iNoCulator™
SignatureIP's cloud-based design platform, iNoCulator™, enables engineering teams to architect, configure and generate coherent and non-coherent networks-on-chip for chiplet-based systems. The platform streamlines what has traditionally been one of the most complex and time-consuming steps in chiplet system design, allowing teams to iterate on topology, coherency and bandwidth trade-offs in the cloud rather than in bespoke, in-house flows.
Interface IP: PCIe, CXL and Ethernet
The library includes silicon-proven interface IP for PCIe, CXL and Ethernet, giving customers the die-to-die and off-package connectivity needed to move data reliably between chiplets, host processors, accelerators and the network at the throughput AI and HPC systems demand.
SoC Subsystem IP: Reference Platforms for Compute, Memory and I/O
SignatureIP's SoC Subsystem IP portfolio includes Ultra-Low-Latency D2D Controller IP for streaming protocols, Proxy Cache and other AMBA-specific bridge blocks. The library supports the design of Compute, Memory and I/O subsystems optimized for minimum wall-clock time and maximum throughput, providing customers with customizable, pre-verified, pre-integrated, prototyped building blocks for the subsystems that make up a modern chiplet-based AI or HPC package.
“AI and HPC customers don’t want to integrate a dozen point IPs from many different vendors and hope they work together on silicon – they want a proven, coherent library purpose-built for chiplets from the ground up. That’s exactly what we’re bringing to the AI Infra Summit this year: Interconnect, Interface and SoC System IP, plus the graphical System Controller Subsystem Builder that ties it all together, enabling customers to progress from architecture to tape-out faster and with far less integration risk,” said Ramana Rao, CTO at SignatureIP.
System Controller Subsystem IP: RISC-V and ARM
Tying the full library together is SignatureIP's System Controller Subsystem IP, available in customizable RISC-V- and ARM-based configurations, which manages and coordinates the Interconnect, Interface and System subsystems across the chiplet-based design.
“SignatureIP and Breker have established a solid partnership developing leading-edge reference design and verification solutions for RISC-V and ARM coherent subsystems that increase quality and save time,” noted Adnan Hamid, CTO, Breker Verification Systems. “Breker’s Coherency, RISC-V and ARM SoCReady SystemVIPs are an excellent complement to SignatureIP’s leading-edge design IP for complex applications, such as AI and HPC devices.”
Representative Chiplet System Architecture
The diagram below illustrates two symmetric chiplets, each combining a Compute Cluster and an I/O Cluster on a single die, and each governed by its own SignatureIP System Controller Subsystem. A shared SignatureIP CXL port on each die multiplexes PCIe, C2C and CXS, enabling the Compute Cluster's Coherent Network-on-Chip (C-NoC) link to its neighbor's Compute Cluster over C2C and the I/O Cluster's Non-Coherent Network-on-Chip (NC-NoC) link to its neighbor's I/O Cluster over CXS — with a SignatureIP Proxy Cache bridging the coherent and non-coherent domains on-die. A SignatureIP 100G Ethernet MAC provides network I/O, while a partner’s solution via a C-NoC enables access to memory resources.
Availability
SignatureIP's Interconnect, Interface and System IP library is available now for evaluation and licensing. SignatureIP will be showcasing the full library, including live demonstrations of the iNoCulator™ platform, at AI Infra Summit 2026, September 15–17 at the Santa Clara Convention Center, Booth #1001.
About SignatureIP
SignatureIP is the pioneer of next-generation silicon infrastructure IP and solutions. Founded in 2021, the company develops advanced network-on-chip and connectivity IP forming the basis for complete SoC platform designs, including PCIe, CXL, Ethernet and NoC IP, alongside custom Compute Subsystem, Memory Subsystem and IO Subsystem chiplet design services. SignatureIP's leadership team brings 120+ person-years of engineering expertise in interconnect, networking, data center, storage and connectivity IP. Headquartered in Milpitas, California with engineering operations across the US, India, Singapore and the Philippines, the company has delivered 32+ successful SoC projects. SignatureIP achieved PCI-SIG® PCIe® 5.0 certification in September 2025. For more information, visit www.signatureip.ai.