Jagjot Kaur
Jagjot is a Tessent Technology Enablement Director for the Tessent product line. She has 20 years of DFT experience with a blend of EDA and design work. She has worked at several technology companies like Freescale Semiconductors, Texas Instruments, Qualcomm, Intel, Cadence Design Systems before joining Siemens EDA. Jagjot has worked on a wide variety of test challenges and designs including semiconductor chips that span from Cellular, Servers and Data Center designs to Graphics, Networking and Aerospace designs. In EDA, Jagjot has worked in several roles including Product Validation, Applications, Solutions and Product Engineering. She holds 5 patents and actively contributes towards reviews of DFT IEEE papers
Sessions
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Power Analysis, Power-Aware Design & Verification Challenges & Innovations for AI Hardware17-Sep-2026Expo Theater 1