Sponsor Editorial

Matrix multiplication is fundamental to AI inference, data preprocessing, scientific computing, and other compute-intensive applications. This article presents practical lessons from implementing and optimizing a double-precision general matrix multiplication, or DGEMM, kernel using the RISC-V Vector Extension on an Andes AX46MPV near cycle-accurate simulator.

The study compares a scalar baseline with progressively optimized RVV implementations while examining the effects of vector length, LMUL, row blocking, register utilization, and memory bandwidth. A straightforward manual RVV implementation delivered a 12× performance improvement over scalar code. Additional tuning increased the gain to more than 150×, while enabling the AX46MPV High Bandwidth Vector Memory feature raised performance to 275× and achieved 92.8% of theoretical peak efficiency.

The results also reveal several important optimization lessons. Compilers may not automatically vectorize complex compute kernels effectively, even when aggressive optimization is enabled. Increasing LMUL can improve the amount of work performed per instruction, but excessive LMUL reduces the number of available logical vector registers and can trigger costly register spills. For the tested DGEMM workload, LMUL=4 with four to six accumulator rows provided the best balance between vector utilization, instruction-level parallelism, and register pressure.

The article demonstrates that achieving near-peak RISC-V vector performance requires more than simply increasing vector width. Developers must balance vector configuration, accumulator blocking, register capacity, and memory bandwidth. With careful tuning, RVV and the Andes AX46MPV provide a scalable and highly efficient foundation for AI, high-performance computing, and other matrix-intensive workloads.