Sponsor Editorial

CHI is how coherent CPU clusters talk to the rest of the SoC. Not just a bus — a full protocol with channels, node types, directory-based state machines, and direct-transfer mechanisms that cut memory latency by bypassing the home node entirely. If your SoC has more than one coherent CPU cluster, CHI is the protocol you're building against.

Here's what the paper covers:
🔹 Why hardware coherency is mandatory — and why broadcast snooping hits a hard ceiling 
🔹 CHI's layered channel model (REQ, RSP, SNP, DAT) and the four node types 
🔹 Directory-based coherency and how it replaces the broadcast model at SoC scale
🔹 DMT, DCT, and DWT — the direct-transfer features that eliminate redundant hops 
🔹 CHI revision history: what changed from B through E.b, and why it matters for IP selection 
🔹 The system problems CHI introduces — I/O coherency mismatch, AXI isolation, chiplet latency 
🔹 SignatureIP's full answer: C-NOC, NC-NOC, Proxy Cache, ATC, AXI2CHI, CHI2AXI, Ethernet IP, Inoculator, PCIe Controller, CXL Controller, and CXL Subsystem