Workshops

In the new era of AI infrastructure, CMOS scaling remains the workhorse for heavy computational workloads. But the need for an energy-efficient solution imposes a paradigm shift at the interconnect level, requiring an intimate 3D co-integration of advanced ASICs and optical connectivity. As the architectural complexity of new products increases, relying on state-of-the-art platforms, with a short path to manufacturing. In this workshop, we will highlight how you can access following technologies for your future products:  Advanced-node ASIC down to TSMC N2 Imec’s integrated photonics platforms from 200G up to co-packaged optics Imec’s advanced 3D packaging technique from interposer to hybrid bonding Location: Room 207Duration: 1 hour