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- Start software validation early using hardware models, then continuously co-verify through RTL implementation.
- AI infrastructure needs hardware-software co-design from the outset: software development must begin against virtual hardware models early then through to RTL & physical implementation.
- Compute efficiency requires full-stack software, hardware & microarchitecture co-design & verification throughout deployment.
- Successful AI chip companies must deliver complete systems not isolated silicon: product development must account for power delivery, cooling, networking, software & data centre integration.
- AI is becoming both the workload & the design tool: Machine Learning, Reinforcement Learning & agentic workflows can help manage growing system complexity.
Sandeep Mehndiratta, SVP - AI Partnerships, Synopsys; Usman Ali, Senior ASIC Engineer – Architecture, Meta; Robert Wachen, Co-Founder & President, Etched; Andy Hock, Chief Strategy Officer, Cerebras; Jonathan Pearce, Co-Founder & Chief Architect, AheadComputing Inc.
Marshall Choy, Chief Business Officer, Rebellions
- Sovereign AI requires on-premises deployment at scale for resilience, independence & infrastructure control.
- Large-scale inference favours hetergenous compute, matching silicon & systems to each workload’s business outcome.
- Government sovereign AI needs secure air-gapped, rack-scale infrastructure orchestrated through open-source platforms.
- Production inference demands predictable latency, reliability, burst capacity & measurable business outcomes beyond benchmarks.
- Performance per dollar & watt optimisation becomes essential as inference deployments expand & operating costs increase.
- Inference hardware choices must follow workloads: agentic, enterprise, LLM & multimodal workloads each require different balances of CPUs, accelerators, memory & networking.
- Memory is becoming AI infrastructure’s defining bottleneck: energy & cost limits are creating demand for new 3D memory technologies & chiplet-based integration.
- Agentic AI requires more than fast inference: tool use, retrieval, web search & orchestration favour more integrated CPU-accelerator architectures.
- The future of infrastructure will be heterogenous, combining diverse processors, memory technologies, GPUs & endpoint deployments.
- Hardware must combine fixed efficiency with software flexibility: core compute, connectivity, bandwidth & power efficiency should be hardened with silicon, while programmability supports rapidly changing models.
David Goldman, Partner, Celesta Capital; Chloe Ma, Chief Business Officer, Epic Semi; Anton McGonnell, VP Product, SambaNova Systems; Sylvain Dubois, Co-Founder & CEO, Vertical Compute; Kamran Khan, Head of BD/GTM Annapurna ML, AWS
Juan Carlos Rey, CTO, Siemens EDA
- Chiplets & 2.5D/3D integration are becoming critical to scaling AI compute.
- Complex designs require full-stack validation across microarchitecture, software & hardware rather than just isolated component testing.
- Early virtual hardware models let teams co-develop software & validate architectures before RTL completion.
- Digital twins can connect design decisions across the development lifecycle.
- AI is both driving compute demand & helping design the systems that meet it – AI models & agentic workflows can accelerate architecture, floor planning & physical design, with verification remaining essential before manufacture.
- AI’s economic viability depends on the cost & revenue of serving additional inference: infrastructure & training costs are increasing, so more revenue must be made per user or token.
- Inference needs different architectures for different stages of computation & hardware that matches requirements improves user responsiveness & operational efficiency.
- Heterogenous systems can exploit the complementary strengths of GPUs & specialised accelerators.
- Disaggregation improves utilisation, but communication overhead limits scaling efficiency in large deployments.
- Inference success requires balancing responsiveness, throughput & energy consumption.
Satyam Srivastava, Distinguished Engineer, d-Matrix